Chapter 2
Instruction Set
2.1) Introduction
The first thing to be done when designing a processor is to decide which
instructions we are going to implement. To make our processor as general as
possible, we have chosen to include the most common instructions from
various other processors that are around today.
A summary of the ARM7 instruction set is shown in Figure (2-1)
Figure (2-1): Instruction Set Summary
2.2) The Condition Field
All ARM instructions are conditionally executed, which means that their
execution may or may not take place depending on the values of the N, Z, C
and V flags in the CPSR. The condition encoding is shown in Figure (2-2).
If the always (AL) condition is specified, the instruction will be executed
irrespective of the flags. The never (NV) class of condition codes shall
not be used as they will be redefined in future variants of the ARM
architecture. If a NOP is required it is suggested that MOV R0, R0 be used.
The assembler treats the absence of a condition code as though always had
been specified.
The other condition codes have meanings as detailed in Figure (2-2). for
instance code 0000 (EQual) causes the instruction to be executed only if
the Z flag is set. This would correspond to the case where a compare (CMP)
instruction had found the two operands to be equal. If the two operands
were different, the compare instruction would have cleared the Z flag and
the instruction will not be executed.
Figure (2-2): Condition Codes
2.3) Branch and Branch with link (B, BL)
The instruction is only executed if the condition is true. The various
conditions are defined at the beginning of this chapter. The instruction
encoding is shown in Figure (2-3).
Branch instructions contain a signed 2's complement 24 bit offset. This is
shifted left two bits, sign extended to 32 bits, and added to the PC. The
instruction can therefore specify a branch of +/- 32Mbytes. The branch
offset must take account of the prefetch operation, which causes the PC to
be 2 words (8 bytes) ahead of the current instruction.
Branches beyond +/- 32Mbytes must use an offset or absolute destination
that has been previously loaded into a register. In this case the PC should
be manually saved in R14 if a Branch with Link type operation is required.
2.3.1) The link bit
Branch with Link (BL) writes the old PC into the link register (R14) of the
current bank. The PC value written into R14 is adjusted to allow for the
prefetch, and contains the address of the instruction following the branch
and link instruction. Note that the CPSR is not saved with the PC. To
return from a routine called by Branch with Link use MOV PC,R14 if the link
register is still valid or LDM Rn!,{..PC} if the link register has been
saved onto a stack pointed to by Rn.
Figure (2-3): Branch Instructions
2.4) Data processing
The instruction is only executed if the condition is true, defined at the
beginning of this chapter. The instruction encoding is shown in Figure (2-
4).
The instruction produces a result by performing a specified arithmetic or
logical operation on one or two operands. The first operand is always a
register (Rn). The second operand may be a shifted register (Rm). The
condition codes in the CPSR may be preserved or updated as a result of this
instruction, according to the value of the
S bit in the instruction. Certain operations (TST, TEQ, CMP, CMN) do not
write the result to Rd. They are used only to perform tests and to set the
condition codes on the result and always have the S bit set. The
instructions and their effects are listed in Table (2-1)
2.4.1) CPSR flags
The data processing operations may be classified as logical or arithmetic.
The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the
logical action on all corresponding bits of the operand or operands to
produce the result. If the S bit is set (and Rd is not R15, see below) the
V flag in the CPSR will be unaffected, the C flag will be set to the carry
out from the barrel shifter (or preserved when the shift operation is LSL
#0), the Z flag will be set if and only if the result is all zeros, and the
N flag will be set to the logical value of bit 31 of the result.
The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat
each operand as a 32-bit integer (either unsigned or 2's complement signed,
the two are equivalent). If the S bit is set (and Rd is not R15) the V flag
in the CPSR will be set if an overflow occurs into bit 31 of the result;
this may be ignored if the operands were considered unsigned, but warns of
a possible error if the operands were 2's complement signed. The C flag
will be set to the carry out of bit 31 of the ALU, the Z flag will be set
if and only if the result was zero, and the N flag will be set to the value
of bit 31 of the result (indicating a negative result if the operands are
considered to be 2's complement signed).
Figure (2-4): Data Processing Instructions
2.4.2) Shifts
When the second operand is specified to be a shifted register, the Shift
field in the instruction controls the operation of the barrel shifter. This
field indicates the type of shift to be performed (logical left or right,
arithmetic right or rotate right). The amount by which the register should
be shifted may be contained in an immediate field in the instruction, or in
the bottom byte of another register (other than R15). The encoding for the
different shift types is shown in Figure (2-5).
Assembler
Mnemonic | OpCode | Action |
|---|
| AND | 0000 | operand1 AND operand2 |
| EOR | 0001 | operand1 EOR operand2 |
| SUB | 0010 | operand1 - operand2 |
| RSB | 0011 | operand2 - operand1 |
| ADD | 0100 | operand1 + operand2 |
| ADC | 0101 | operand1 + operand2 + carry |
| SBC | 0110 | operand1 - operand2 + carry - 1 |
| RSC | 0111 | operand2 - operand1 + carry - 1 |
| TST | 1000 | as AND, but result is not written |
| TEQ | 1001 | as EOR, but result is not written |
| CMP | 1010 | as SUB, but result is not written |
| CMN | 1011 | as ADD, but result is not written |
| ORR | 1100 | operand1 OR operand2 |
| MOV | 1101 | operand2 (operand1 is ignored) |
| BIC | 1110 | operand1 AND NOT operand2 (Bit clear) |
| MVN | 1111 | NOT operand2 (operand1 is ignored) |
Table (2-1): ARM Data Processing Instructions
Figure (2-5): ARM Shift Operations
2.4.3) Immediate operand rotates
The immediate operand rotate field is a 4 bit unsigned integer which
specifies a shift operation on the 8 bit immediate value. This value is
zero extended to 32 bits, and then subject to a rotate right by twice the
value in the rotate field. This enables many common constants to be
generated, for example all powers of 2.
2.4.4) Writing to R15
When Rd is a register other than R15, the condition code flags in the CPSR
may be updated from the ALU flags as described above.
When Rd is R15 and the S flag in the instruction is not set the result of
the operation is placed in R15 and the CPSR is unaffected.
When Rd is R15 and the S flag is set the result of the operation is placed
in R15 and the SPSR corresponding to the current mode is moved to the CPSR.
This allows state changes that atomically restore both PC and CPSR. This
form of instruction shall not be used in User mode.
2.4.5) Using R15 as an operand
If R15 (the PC) is used as an operand in a data processing instruction the
register is used directly.
The PC value will be the address of the instruction, plus 8 bytes due to
instruction prefetching.
2.4.6) TEQ, TST, CMP & CMN opcodes
These instructions do not write the result of their operation but do set
flags in the CPSR.
2.5) PSR Transfer (MRS, MSR)
The instruction is only executed if the condition is true. The various
conditions are defined at the beginning of this chapter.
The MRS and MSR instructions are formed from a subset of the Data
Processing operations and are implemented using the TEQ, TST, CMN and CMP
instructions without the S flag set. The encoding is shown in Figure (2-6).
These instructions allow access to the CPSR and SPSR registers. The MRS
instruction allows the contents of the CPSR or SPSR_<mode> to be moved to a
general register. The MSR instruction allows the contents of a general
register to be moved to the CPSR or SPSR_<mode> register.
2.5.1) Operand restrictions
In User mode, the control bits of the CPSR are protected from change, so
only the condition code flags of the CPSR can be changed. In other
(privileged) modes the entire CPSR can be changed.
The SPSR register that is accessed depends on the mode at the time of
execution. For example, only SPSR_fiq is accessible when the processor is
in FIQ mode.
R15 shall not be specified as the source or destination register.
A further restriction is that no attempt shall be made to access an SPSR in
User mode, since no such register exists.
Figure (2-6): PSR Transfer
2.6) Multiply and Multiply-Accumulate (MUL, MLA)
The instruction is only executed if the condition is true. The various
conditions are defined at the beginning of this chapter. The instruction
encoding is shown in Figure (2-7).
The multiply and multiply-accumulate instructions use a 3 bit modified
Booth's algorithm to perform integer multiplication. They give the least
significant 32 bits of the product of two 32-bit operands, and may be used
to synthesize higher precision multiplications.
The multiply form of the instruction gives Rd:=Rm*Rs. Rn is ignored, and
should be set to zero for compatibility with possible future upgrades to
the instruction set. The multiply-accumulate form gives Rd:=Rm*Rs+Rn, which
can save an explicit ADD instruction in some circumstances.
Figure (2-7): Multiply Instructions
2.6.1) CPSR flags
Setting the CPSR flags is optional, and is controlled by the S bit in the
instruction. The N (Negative) and Z (Zero) flags are set correctly on the
result (N is made equal to bit 31 of the result, and Z is set if and only
if the result is zero). The C (Carry) flag is set to a meaningless value
and the V (oVerflow) flag is unaffected.
2.7) Single data transfer (LDR, STR)
The instruction is only executed if the condition is true. The various
conditions are defined at the beginning of this chapter. The instruction
encoding is shown in Figure (2-8).
The single data transfer instructions are used to load or store single
bytes or words of data. The memory address used in the transfer is
calculated by adding an offset to a base register.
Figure (2-8): Single Data Transfer Instructions
2.7.1) Use of R15
When using R15 as the base register you must remember it contains address 8
bytes on from the address of the current instruction.
When R15 is the source register (Rd) of a register store (STR) instruction,
the stored value will be address of the instruction plus 8.
2.8) Block data transfer (LDM, STM)
The instruction is only executed if the condition is true. The various
conditions are defined at the beginning of this chapter. The instruction
encoding is shown in Figure (2-9).
Block data transfer instructions are used to load (LDM) or store (STM) any
subset of the currently visible registers. They support all possible
stacking modes, maintaining full or empty stacks that can grow up or down
memory, and are very efficient instructions for saving or restoring
context, or for moving large blocks of data around main memory.
2.8.1) Register list
The instruction can cause the transfer of any registers in the current bank
(and non-user mode programs can also transfer to and from the user bank,
see below). The register list is a 16-bit field in the instruction, with
each bit corresponding to a register. A 1 in bit 0 of the register field
will cause R0 to be transferred, a 0 will cause it not to be transferred;
similarly bit 1 controls the transfer of R1, and so on.
Any subset of the registers, or all the registers, may be specified. The
only restriction is that the register list should not be empty.
Whenever R15 is stored to memory the stored value is the address of the STM
instruction plus 8.
Figure (2-9): Block Data Transfer Instructions
2.8.2) Address Alignment
The address should normally be a word aligned quantity and non-word aligned
addresses do not affect the instruction. However, the bottom 2 bits of the
address will appear on A[1:0] and might be interpreted by the memory
system.
2.9) Software interrupt (SWI)
Figure (2-10): Software Interrupt Instruction
The instruction is only executed if the condition is true. The various
conditions are defined at the beginning of this chapter. The instruction
encoding is shown in Figure (2-10).
The software interrupt instruction is used to enter Supervisor mode in a
controlled manner. The instruction causes the software interrupt trap to be
taken, which effects the mode change. The PC is then forced to a fixed
value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address
is suitably protected (by external memory management hardware) from
modification by the user, a fully protected operating system may be
constructed.
2.9.1) Return from the supervisor
The PC is saved in R14_svc upon entering the software interrupt trap, with
the PC adjusted to point to the word after the SWI instruction. MOVS PC,
R14_svc will return to the calling program and restore the CPSR.
Note that the link mechanism is not re-entrant, so if the supervisor code
wishes to use software interrupts within itself it must first save a copy
of the return address and SPSR.
2.9.2) Comment field
The bottom 24 bits of the instruction are ignored by the processor, and may
be used to communicate information to the supervisor code. For instance,
the supervisor may look at this field and use it to index into an array of
entry points for routines that perform the various supervisor functions.
2.10) Undefined instruction
Figure (2-11): Undefined Instruction
The instruction is only executed if the condition is true. The various
conditions are defined at the beginning of this chapter. The instruction
format is shown in Figure (2-11).
If the condition is true, the undefined instruction trap will be taken.
Note that the undefined instruction mechanism involves offering this
instruction to any coprocessors that may be present, and all coprocessors
must refuse to accept it by driving CPA and CPB HIGH.