Control unit signals

Control unit signals
Instr	rs1_sel	rs2_sel	rs3_sel	ws_sel	wd_sel	nwe_regfile	mode_regfile	nwe_PC	inc_PC	PC_sel	vector_sel	pc_bkup_sel	nwe_MDRR	nwe_MDRW	nMREQ	nENOUT	SEQ	nOPC	nCPI	nRW	nwe_MAR	MAR_sel	nwe_IR	IR_sel	nwe_IR_prefetch	rst_prefetch	nwe_priority	next_priority	B_sel	val_sel	fn_shifter	fn_ALU	ALU_sel	start_mul	C_sel	S_sel	SV_sel	set_fiq	set_irq	backup_psr	restore_psr	new_mode	we_mode	psr_in_sel	ld_psr	rd_psr
reset1
phase1
phase2								0		vector	0x0
reset2
phase1								0		vector	0x0																											1	1			10011	1
phase2																																						1	1			10011	1
int1
phase1																										1														1		10001: if nFIQ, else 10010: if nIRQ
phase2				R14	PC_out	0	1																			1														1		10001: if nFIQ, else 10010: if nIRQ
int2
phase1				R14	PC_out	0	1																															1: if nFIQ	1			10001: if nFIQ, else 10010: if nIRQ	1
phase2								0		vector	0x1C: if nFIQ, else 0x18: if nIRQ																											1: if nFIQ	1			10001: if nFIQ, else 10010: if nIRQ	1
abt
phase1				R14	PC_out	0	1																			1													1			10111	1
phase2								0		vector	0x10 if data, else 0x0c if fetch															1													1			10111	1
fetch
T1_phase1								0: if nFIQ or nIRQ or ABORT		vector: if nFIQ or nIRQ or ABORT	0x10 if data_abt, else 0x1C: if nFIQ, else 0x18: if nIRQ,else 0x0C: if fetch_abt				0						0	PC_out	if empty_prefetch=0: 0	if empty_prefetch=0: IR
T1_phase2									if !(empty_prefetch=0 & bad_prefetch=1): 1						0			0		0	0	PC_out	if empty_prefetch=0: 0	if empty_prefetch=0: IR
decode
T2_phase1									if !(empty_prefetch=0 & bad_prefetch=1): 1						if empty_prefetch=1: 0			0		0	if empty_prefetch=1: 0	if empty_prefetch=1: PC_out	if empty_prefetch= 1: 0	if empty_prefetch=1: mem	if empty_prefetch=0: 0															if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): 1		if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): 10111
T2_phase2				if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): R14	if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): PC_out	if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): 0	if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): 1		if empty_prefetch: 1						if empty_prefetch=1: 0			if empty_prefetch=1: 0		if empty_prefetch=1: 0	if empty_prefetch=1: 0	if empty_prefetch=1: PC_out	if empty_prefetch=1: 0	if empty_prefetch=1: mem	if empty_prefetch=0: 0															if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): 1		if (ABORT=1 & empty_prefetch=1) or (bad_prefetch=1 & empty_prefetch=0): 10111
T3_phase1									if empty_prefetch: 1						if empty_prefetch=1: 0			if empty_prefetch=1: 0		if empty_prefetch=1: 0					if empty_prefetch=1: 0
T3_phase2																									if empty_prefetch=1: 0
data processing
T2_phase2	IR_out[19:16]	IR_out[3:0]	IR_out[11:8]																										if imm_operand: imm_data, else: rd2	if imm_operand: imm_shift, else: IR_out[11:7]	if imm_operand: ROR, else: IR_out[6:5]
T3_phase1	IR_out[19:16]	IR_out[3:0]	IR_out[11:8]																										if imm_operand: imm_data, else: rd2	if imm_operand: imm_shift, else: IR_out[11:7]	if imm_operand: ROR, else: IR_out[6:5]	IR_out[24:21]	ALU		cout_shifter:if logic instr(AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) cout_ALU: if arithmetic(the rest)	if Rd!=PC: IR_out[20]	1: if arithmetic operation
T3_phase2	IR_out[19:16]	IR_out[3:0]	IR_out[11:8]	IR_out[15:12]	ALU_out	0: if not a test instr.(CMN,CMP,TEQ,TST)																							if imm_operand: imm_data, else: rd2	if imm_operand: imm_shift, else: IR_out[11:7]	if imm_operand: ROR, else: IR_out[6:5]	IR_out[24:21]	ALU		cout_shifter:if logic instr(AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) cout_ALU: if arith(the	if Rd!=PC: IR_out[20]	1: if arithmetic operation
T4_phase1	IR_out[19:16]	IR_out[3:0]	IR_out[11:8]	IR_out[15:12]	ALU_out	0: if not a test instr.(CMN,CMP,TEQ,TST)																							if imm_operand: imm_data, else: rd2	if imm_operand: imm_shift, else: IR_out[11:7]	if imm_operand: ROR, else: IR_out[6:5]	IR_out[24:21]	ALU
T4_phase2	IR_out[19:16]	IR_out[3:0]	IR_out[11:8]		ALU_out
T5_phase1																																									if Rd=PC & mode=user & S=1: 1
T5_phase2																																									if Rd=PC & mode=user & S=1: 1
MRS
T2_phase2				IR_out[15:12]	PSR	0																																								1
T3_phase1				IR_out[15:12]	PSR	0																																								1
MSR
T2_phase2		IR_out[3:0]
T3_phase1		IR_out[3:0]																																										1	1
T3_phase2																																												1	1
LDR
T2_phase2	IR_out[19:16]
T3_phase1	IR_out[19:16]														0						0	ALU_out							extend	0	0	0010: if U=0, 0100: if U=1	ALU
T3_phase2	IR_out[19:16]														0					0	0	ALU_out							extend	0	0	0010: if U=0, 0100: if U=1	ALU
T4_phase1													if ABORT = 0: 0							0																				if ABORT: 1		if ABORT: 10111
T4_phase2				if ABORT=0: IR_out[15:12]	if ABORT=0: MDRR	if ABORT=0: 0							if ABORT = 0: 0																											if ABORT: 1		if ABORT: 10111
T5_phase1				if ABORT=0: IR_out[15:12]	if ABORT=0: MDRR	if ABORT=0: 0																																									if ABORT: goto abt
T5_phase2				if ABORT: R14	if ABORT: PC_out	if ABORT: 0	if ABORT: 1																																			if ABORT: 10111
STR
T2_phase2	IR_out[19:16]	IR_out[15:12]
T3_phase1	IR_out[19:16]	IR_out[15:12]												0	0						0	ALU_out							extend	0	0	0010: if U=0, 0100: if U=1	ALU
T3_phase2	IR_out[19:16]	IR_out[15:12]												0	0	0				1	0	ALU_out							extend	0	0	0010: if U=0, 0100: if U=1	ALU
T4_phase1																0				1																				if ABORT: 1		if ABORT: 10111
T4_phase2																																								if ABORT: 1		if ABORT: 10111
T5_phase1
T5_phase2				if ABORT: R14	if ABORT: PC_out	if ABORT: 0	if ABORT: 1																																			if ABORT: 10111					if ABORT: goto abt
B,BL
T2_phase2				R14: if BL	PC_out: if BL	0: if BL
T3_phase1				R14: if BL	PC_out: if BL	0: if BL
T3_phase2								0		adder
T4_phase1								0		adder
SWI
T2_phase2				R14	PC_out	0	1																																			10011
T3_phase1				R14	PC_out	0	1																																	1		10011
T3_phase2								0		vector	0x8																													1		10011
T4_phase1								0		vector	0x8																												1			10011	1
T4_phase2																																							1			10011	1
T5_phase1
T5_phase2
MUL,MLA
T2_phase2	IR_out[11:8]	IR_out[3:0]	IR_out[15:12]
T3_phase1	IR_out[11:8]	IR_out[3:0]	IR_out[15:12]																															1
T3_phase2	IR_out[11:8]	IR_out[3:0]	IR_out[15:12]																															1
T4_phase1	IR_out[11:8]	IR_out[3:0]	IR_out[15:12]																														MUL
T4_phase2	IR_out[11:8]	IR_out[3:0]	IR_out[15:12]	if fin_mul: IR_out[19:16]	if fin_mul: ALU_out	if fin_mul: 0																											MUL														en_ring=off: if fin_mul = 0
T5_phase1	IR_out[11:8]	IR_out[3:0]	IR_out[15:12]	if fin_mul: IR_out[19:16]	if fin_mul: ALU_out	if fin_mul: 0																											MUL			IR_out[20]
T5_phase2	IR_out[11:8]	IR_out[3:0]	IR_out[15:12]																														MUL			IR_out[20]
LDM
T2_phase2	IR_out[19:16]
T3_phase1	IR_out[19:16]														0						0	rd1: if U=1 ALU_out: if U=0					0		reg_count	2	0	0010	ALU
T3_phase2															0					0	0	rd1: if U=1 ALU_out: if U=0					0		reg_count	2	0	0010	ALU
T4_phase1													if ABORT=0: 0							0																				if ABORT: 1		if ABORT: 10111
T4_phase2				if ABORT=0: priority	if ABORT=0: MDRR	if ABORT=0: 0							if ABORT=0: 0																											if ABORT: 1		if ABORT: 10111
T5_phase1				if ABORT=0: priority	if ABORT=0: MDRR	if ABORT=0: 0									0		1											1
T5_phase2				if ABORT & fin_priority: R14	if ABORT & fin_priority: PC_out	if ABORT & fin_priority: 0	if ABORT & fin_priority : 1								0: if fin_priority=0		1: if fin_priority=0			0: if fin_priority=0								1														if ABORT: 10111					LD_ring=T5, nwe_ring=0: if fin_priority=0,else if ABORT & fin_priority: goto abt
STM
T2_phase2	IR_out[19:16]
T3_phase1	IR_out[19:16]																				0	rd1: if U=1 ALU_out: if U=0					0		reg_count	2	0	0010	ALU
T3_phase2		priority																			0	rd1: if U=1 ALU_out: if U=0					0		reg_count	2	0	0010	ALU
T4_phase1		priority												0	0																									if ABORT: 1		if ABORT: 10111
T4_phase2														0	0	0				1																				if ABORT: 1		if ABORT: 10111
T5_phase1																0	1			1								1
T5_phase2				if ABORT & fin_priority: R14	if ABORT & fin_priority: PC_out	if ABORT & fin_priority: 0	if ABORT & fin_priority : 1										1: if fin_priority=0											1														if ABORT & fin_priority: 10111					LD_ring=T5, nwe_ring=0: if fin_priority=0,else if ABORT & fin_priority: goto abt
undefined
T2_phase2																			0
T3_phase1																			0
T3_phase2				if CPA=1: R14	if CPA=1: PC_out	if CPA=1: 0	if CPA=1: 1												if CPA=0 & CPB=1: 0																							if CPA=1: 11011
T4_phase1				if CPA=1: R14	if CPA=1: PC_out	if CPA=1: 0	if CPA=1: 1												if CPA=0 & CPB=1: 0																					if CPA=1: 1		if CPA=1: 11011
T4_phase2								if CPA=1: 0		vector	0x04								if CPA=0 & CPB=1: 0																					if CPA=1: 1		if CPA=1: 11011
T5_phase1								if CPA=1: 0		vector	0x04								if CPA=0 & CPB=1: 0																				1			if CPA=1: 11011	1
T5_phase2																			if CPA=0 & CPB=1: 0																				1			if CPA=1: 11011	1				if CPA=0 & CPB=1: en_ring = off